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March 19, 2014

Yamaha Reduces Power Leakage by Half in Its Mobile Chips

Size and power are two critical components in computing that determine how a product is going to be manufactured. As the computing devices we use keep getting smaller and smaller, manufacturers have to develop new technologies that are able to use the available power with more efficiency.

Power leakage in portable devices such as smartphones, tablets and M2M modules is a great concern for everyone in the value chain. Whether it is chip manufacturers, software developers or service providers, they all want to ensure consumers have the longest available time with every charge. In order to improve its reduction of power leakage, Yamaha Corporation has employed different components from the Cadence Low-Power Solution in its newest chips for smartphones.

According to Cadence Design Systems Inc., Yamaha has implemented Cadence Encounter RTL Compiler (RC), Cadence Encounter Conformal Low Power (CLP) and Cadence Encounter Digital Implementation (EDI) System, which has resulted in reducing power leakage by 50 percent in its mobile chips.

The technology Cadence uses provides multiple solutions supporting advanced low-power techniques including multi-supply voltage, power shutoff and multi-bit cell inferencing to reduce power. The Cadence software, hardware, IP, and services are used by customers across different industries to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems.

The Encounter RTL Compiler delivers faster runtimes with a breakthrough synthesis algorithm, efficient data structures and modern programming techniques allowing for multiple design applications with the best speed, area, and power after physical implementation.

Some of the key features of this platform include:

  • A well-balanced logic structure isolates critical paths, reduces power, area, and congestion in off-critical logic, and enables faster timing closure and design convergence through place and route
  • Spatial technology eliminates the need for wireload models by modeling physical interconnect at a higher level of abstraction for use in RTL-to-gate optimization
  • Reduces power consumption through single-pass multi-Vt optimi­zation, hierarchical and multi-stage clock gating, true top-down multi-supply voltage exploration and synthesis, and full power shutoff support with the Common Power Format (CPF)
  • Shrinks die sizes with multi-objective optimization, which creates smaller logic structures for non-timing-critical regions
  • Multi-mode synthesis optimization and analysis accelerates overall turnaround time to design closure for complex chips with multiple functional modes

Additional benefits of this platform includes super threading technology which leads to superior runtimes, quicker turnaround times and faster converges on design goals. With the built-in design quality analyzer in place it is able to identify pre-synthesis design issues which may lead to suboptimal or unintended results.

"Low power is critical for our new mobile chip designsBecause the tools in the Cadence Low-Power Solution support the Common Power Format, it allowed us to leverage advanced power management techniques, which resulted in better power and performance and shorter turnaround time for our design," said Shuhei Ito, development director for Yamaha Corporation.

Edited by Alisen Downey

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